1. Field of the Invention
The present invention relates to a structure of an IC device and fabrication of the same. More particularly, the present invention relates to a capacitor structure and a method for fabricating the same.
2. Description of the Related Art
As the integration degree of semiconductor devices is greatly increased, the sizes of the same are much reduced. Since the space for forming capacitors are also much reduced correspondingly, the capacitors have insufficient capacitance. This problem is particularly significant in deep sub-micron processes.
There are three categories of capacitors in general, including metal-insulator-metal (MIM) capacitor, metal-line to metal-line (MOM) capacitor and metal-insulator-silicon (MIS) capacitor. MIM capacitors and MOM capacitors are widely used in deep sub-micron IC products, but adversely have lower unit-area capacitance.
A method to increase the capacitance is to decrease the thickness of the dielectric film between the electrodes, but the uniformity and stability of a thin dielectric film is difficult to control. Another method is to form 3D electrodes with larger surface areas, but the forming process is quite complicated making the mass production difficult. Still another method is to use a high-k material to achieve higher unit-area capacitance, but the reliability of such a capacitor is often insufficient.
FIGS. 1A-1C illustrate, in a cross-sectional view, a process flow of fabricating a capacitor structure in the prior art. Referring to FIG. 1A, a substrate 100 including a capacitor area 101 and a conductive line area 103 is provided, wherein the substrate 100 in the area 103 has been formed with a conductive line 102 therein. Then, a metal layer 104, an insulating layer 106 and another metal layer 108 are sequentially formed over the substrate 100 in the capacitor area 101.
Referring to FIG. 1B, a first patterning step is conducted to remove a portion of each of the metal layer 108 and the insulating layer 106 to form an upper electrode 108a and a patterned insulating layer 106a. A second patterning step is then conducted to remove a portion of the metal layer 104 to form a lower electrode 104a and finish the fabricating process of a capacitor 10.
Referring to FIG. 1C, a dielectric layer 110 is formed over the substrate 100, a third patterning step is conducted to form contact openings 112, 114 and 116, and then metal is filled into the contact openings 112-116 to form contact plugs 112a, 114a and 116a connected with the upper electrode 108a, the lower electrode 104a and the conductive line 102, respectively.
However, because the forming processes of the upper electrode 108a and the lower electrode 104a cannot be integrated with other semiconductor processes, two extra photomasks are needed making the above method complicated and costly.
Moreover, since the contact plugs 112a, 114a and 116a are connected to the upper electrode 108a, the lower electrode 104a and the conductive line 102 respectively, the contact openings 112-116 have different depths. Hence, in the etching stage of the third patterning step, either the deeper contact opening 116 is formed insufficiently deep or the shallower contact openings 112 and 114 overly etched to damage the electrodes.
On the other hand, though the capacitance of such a capacitor 10 can be raised by increasing the lateral areas of the upper electrode 108a, the insulating layer 106a and the lower electrode 104a, the integration degree of devices is reduced by doing so.